;****************************************************************
;		 MCGenjin PC-Engine Memory Mapper		*
;****************************************************************
; MCGenjin is a memory mapper for the PC-Engine console which
; is implementable on a single Altera EPM7032LC44 CPLD.
; It supports up to 8MB of ROM and internal swapping of the 
; datalines for region control. Two user chipselect lines are 
; given, each with a 256KB mapping area.
;
; The 1MB cartslot is remapped as:
;	$00000-$3FFFF Low 256KB of ROM
;	$40000-$7FFFF Selected 256KB ROM Bank
;	$80000-$BFFFF User CS0
;	$C0000-$FFFFF User CS1
; Writes to even addresses in $00000-$7FFFF set
; mapper region control. Odd addresses set the
; current 256KB bank.
;                            76543210
;    Mapper Region Control : xxxxxxxS
;      0 = Data line order normal
;      1 = Data line order reversed
;                            76543210
;    Mapper Bank Control   : xxxBBBBB
;      BBBBB = A22-A18 of the 256KB bank address
;    Note that while reads from ROM are reversed
;      when data line transposition is enabled, writes
;      to the mapper remain unaltered.
;
; The most common configuration for the mapper is nonvolatile
; memory (FRAM) attached to CS0, and SRAM attached to CS1.
; Note that in the case of slow ROMs used with MCGenjin, their 
; CE and OE should be enabled either at all times or using a20
; to prevent delay from relying on the mapper's enable line.
;****************************************************************
.define MCGENJIN_REGION	$FFFE
.define REGION_SWAPPED	$FF
.define REGION_USWAPPED $00

.define MCGENJIN_BANK	$FFFF